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LTC1661
4
1661fa
TIMING CHARACTERISTICS The
l
denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
VCC = 2.7V to 5.5V
t1
DIN Valid to SCK Setup
(Note 6)
l
60
ns
t2
DIN Valid to SCK Hold
(Note 6)
l
0
ns
t3
SCK High Time
(Note 6)
l
50
ns
t4
SCK Low Time
(Note 6)
l
50
ns
t5
CS/LD Pulse Width
(Note 6)
l
100
ns
t6
LSB SCK High to CS/LD High
(Note 6)
l
50
ns
t7
CS/LD Low to SCK High
(Note 6)
l
30
ns
t9
SCK Low to CS/LD Low
(Note 6)
l
0
ns
t11
CS/LD High to SCK Positive Edge
(Note 6)
l
30
ns
SCK Frequency
Square Wave (Note 6)
l
10
MHz
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: Nonlinearity and monotonicity are defined from code 20 to code
1023 (full scale). See Applications Information.
Note 3: Digital inputs at 0V or VCC.
Note 4: Load is 10k
Ω in parallel with 100pF.
Note 5: VCC = VREF = 5V. DAC switched between 0.1VFS and 0.9VFS,
i.e., codes k = 102 and k = 922.
Note 6: Guaranteed by design and not subject to test.
TIMING DIAGRAM
DIN
CS/LD
SCK
A3
A2
1661 TD
A1
X1
X0
t2
t9
t11
t5
t7
t6
t1
t3
t4
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